模拟电路版图图形布尔运算及应用.docVIP

 模拟电路版图图形布尔运算及应用# 张龙，蔡懿慈** （清华大学计算机科学与技术系） 5 10 15 20 25 30 35 40 摘要：EDA 领域图形布尔运算的一个重要应用是版图寄生器件的提取。模拟集成电路寄生 效应的存在，使得版图上不可避免地产生各种寄生器件，直接影响集成电路的性能。在集成 电路设计过程中，需要提取寄生器件，进行电路仿真，以便判断这些寄生器件是否对电路性 能造成影响。根据寄生器件产生的机理，通过版图图形的布尔运算，提取集成电路寄生器件。 本文设计和实现针对集成电路版图的图形布尔运算。集成电路集成度的增加，带来版图图形 数据量大，给版图的图形运算带来困难。本文采用扫描线算法的一种变形方法——基于边的 方法，定义 Scanbeam 辅助完成图形布尔运算，该方法能够有效地提高图形的运算速度和处 理能力。 关键词：模拟集成电路；寄生器件提取；图形布尔运算；扫描线算法；Scanbeam 中图分类号：TN791 Graph Boolean Operations for Analog IC Mask and Its Application ZHANG Long, CAI Yici (Department of Computer Science and Technology) Abstract: An important application of Boolean operations on polygons in EDA field is the parasitic extraction in analog integrated circuit layout. There are parasitic effects in integrated circuit. IC process brings a variety of parasitic components inevitably distributed throughout the chip. The presence of parasitic devices may create false logic switches, which make unintended impacts on circuit performance. It is necessary to extract the parasitic device and carry out circuit simulation to determine whether these parasitic components have an effect on circuit performance. Boolean operation on polygons is a core algorithm in extraction of parasitic devices. Corresponding Boolean operations is carried out based on different rules of the parasitic device extraction. In this paper we aimed at designing and implementing the Boolean operations for large number of graphics in an analog IC layout. We use the edge-based method which is derived from plane sweep algorithm. It defines a Scanbeam to help finishing the Polygon Boolean operation. This method can increase the speed of the graphics operation sharply and greatly speed up its processing power. Key words: Analog Integrated Circuitry; Parasitic device extraction; Polygon Boolean operations; Plane sweep technique; Scanbeam 0 引言 模拟集成电路设计流程包括：电路原理图设计，版图绘制，网表提取与仿真，原理图对 照（LVS）。传统的 EDA 工具可以进行版图寄生参数提取，在进行 LVS 之后进行后仿真， 检查寄生参数对电路功能和性能带来的影响。在高压高功率模拟集成电路设计中，部分节点 电压很高，在版图上会带来一些意想不到的