先进芯片封装知识介绍.ppt

AdvancedPackagingTech12020/11/30

OutlinePackageDevelopmentTrend3DPackageWLCSPFlipChipPackage22020/11/30

PackageDevelopmentTrend32020/11/30

SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend42020/11/30

CSPFamilyMemoryCardSiPModulePackageDevelopmentTrend52020/11/30

3DPackage3DPackage62020/11/30

3DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChipWirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP3S-CSPS-etCSPetCSP+S-CSPPS-fcCSP+SCSPPoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2PoPQFN4SS-SCSP72020/11/30

StackedDieTopdieBottomdieFOWmaterilWire82020/11/30

TSVTSV(ThroughSiliconVia) Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.

?A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV92020/11/30

What’sPoPPoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon. PoP102020/11/30

PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology112020/11/30

PoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethickness